1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, particularly, to a method of connecting multi-layered wiring layers.
2. Description of the Related Art
In a semiconductor device using multi-wiring layers, connection of wiring layers is performed in general by making contact holes in an interlayer insulation layer. FIGS. 3A and 3B collectively show an example of the conventional contact structure of a MOS type semiconductor device for connecting a first wiring layer formed of polycrystalline silicon, said first wiring layer providing a gate electrode, to a second wiring layer formed of a metal.
As seen from FIG. 3A, which is a cross sectional view along the channel region of the MOS transistor, a field oxide layer 2 is selectively formed on the surface of a p-type silicon substrate 1 such that the element region of the MOS transistor is surrounded by the field oxide layer 2. As seen from FIG. 3B, which is a plan view, N.sup.+ -type source and drain regions 3 and 4 are formed apart from each other within the element region with the channel region positioned therebetween. A gate electrode 6 formed of polycrystalline silicon is formed above the channel region with a gate oxide layer 5 interposed therebetween. The gate electrode 6 extends to cover partly the field oxide layer 2 and is covered with an interlayer insulation layer 7 formed of silicon dioxide by CVD. Further, an aluminum wiring layer is formed on the interlayer insulation layer 7. A contact hole 8 is formed in the interlayer insulation layer 7 for bringing the aluminum wiring layer into contact with the gate electrode 6. A reactive ion etching (RIE) is employed for forming the contact hole 8 in accordance with miniaturization of the element. In this case, it is necessary to provide an allowance A in the contact portion of the gate electrode 6 as shown in FIG. 3B in view of the deviation in the mask alignment in the step of PEP (photoetcing process) for forming the contact hole. Naturally, the allowance A inhibits miniaturization of the semiconductor device.
Where the allowance A is not provided, it is possible for the contact hole 8 to extend beyond the gate electrode 6 because of the deviation in the mask alignment, as shown in FIG. 4. In this case, the field oxide layer 2 is also etched in the step of RIE, with the result that an aluminum wiring 9 is brought into electric contact with the silicon substrate 1. In other words, short-circuiting takes place.